Part 1b ECAD+Arch Labs - Trouble Shooting
This page will be added to by ECAD Lab demonstrators as issues are found with the new labs.
Debugging the new labs
- Information to come as we encounter issues....
General hints and tips
Quartus won't start
- If Quartus sits on the taskbar doing nothing when you start it, and when you click on the icon pops a window saying 'No network connection available', close this window and run Quartus again. It should start second time around.
- If you get an error about licence servers, call a demonstrator (if it is during Labs) or email Simon Moore (simon dot moore at cl dot cam dot ac dot uk). The license server might need rebooting or your PWF machine may have lost the license server information. If it might be the latter, try another machine.
Help! My design doesn't work! What do I do now?
- If you are simulating your design, have you tried adding some more $display statements to trace state updates?
- If you are synthesizing your design:
- have you simulated your design first to check functional correctness?
- have you checked the timing analysis (the Fmax) for your design to ensure it meets timing?
have you included the tpad_pin_assignments.qsf file in your project (is it on the list in Project->Add to Project)? If not, Quartus will see that no pins are connected and optimise your design away to nothingness! In case of doubt, change toplevel.sv to light LEDs in a recognisable pattern.
Argh! I'm never going to get this finished on time!
- Remember that you can do work outside of the ECAD labs sessions. Use the ECAD lab sessions more to get help.
- If you miss sessions (e.g. due to illness) or you really "just don't get it", we can usually help arrange extra supervision in conjunction with your DoS. For most people, however, the help provided in the ECAD lab session is sufficient.
Synthesis/Compilation takes too long!
- Synthesis does take quite some time since Quartus has to find a good solution to several NP-Complete problems. In particular, the place and route phase is very complex for larger designs. We've tried to reduce the need to synthesize designs by making good use of simulation.
Quartus seems to have programmed my FPGA with an old version
In the programming window, check that the program file is set tp <top-level name>.sof in the current project directory. You can check and modify this by double clicking on the filename.
Eclipse can't load my program onto the NIOS
- Make sure that your C code is actually compiling and doesn't have any errors
- Check that you have the pins file included in your Quartus project (see above).
- Any time you changed your Qsys setup, re-generate it in Qsys then re-compile the BSP in Eclipse
Check that your Qsys design matches the one in the "lab's picture":
- Make sure there are no address conflicts in Qsys
- Reset your tPad and re-download the .sof file from the Quartus programmer