Part 1b ECAD+Arch Labs - Trouble Shooting
This page will be added to by ECAD Lab demonstrators as issues are found with the new labs.
Before installing guest additions
Ubuntu needs you to run this
sudo apt-get install build-essential linux-headers-`uname -r` dkms
or you miss some essential part, and its "generic build" doesn't give you shared folders support.
Debugging the new labs
- Information to come as we encounter issues....
RISC-V tools not found
riscv32-unknown-elf-as -c -o main.o main.s make: riscv32-unknown-elf-as: No such file or directory make: *** [main.o] Error 1
means they failed to source the setup.bash script in their terminal as described in the instructions
Debouncer testbench error
There was an error in the debouncer testbench script (tb_debounce.do) that compiled
This should be:
This was only present for about 20 hours, but some people have downloaded in that time.
Pins file voltage clashes
The de1soc_pin_assignments.qsf file was missing some voltage settings, which caused builds to fail. This is now fixed - re-download the file.
VirtualBox graphics slow/corrupted
Corrupted graphics means 3D or 2D acceleration is enabled in VirtualBox. Turn it off, it doesn't work.
Unity can be slow without 3D acceleration on some machines - the solution is to disable Unity 3D features, eg: https://ksearch.wordpress.com/2014/05/15/disable-unity-animations/ http://askubuntu.com/questions/289677/how-to-improve-performance-of-virtualbox-when-unity-low-gfx-mode-is-not-working
Don't put your files in shared folders
Quartus will randomly hang if the project lives in a shared folder: VirtualBox probably gets filesystem locking wrong in some way causing concurrency fun. Don't do it.
Quartus doesn't detect DE1-SoC
In the shipped VM the 'Altera DE-SoC' USB map is too restrictive - it's keyed on serial number.
Go into the VM settings, Ports, USB. Select Altera DE-SoC , click on USB plug with orange circle (right hand side). This is a filter to match USB devices. Clear all the boxes except Name, Vendor ID and Product ID. (clearing Product ID as well may work). OK.
No 'Devices' (or other) menu in VirtualBox
Lack of a VirtualBox 'Devices' menu on a VM prevents attaching guest additions, shared folders, USB, etc
Spotted on a Mavericks Mac on VBox 5.0.6: highlight VirtualBox control panel window, go to menu bar, VirtualBox -> Preferences, go to User Interface, ensure all tabs are shaded. Any unshaded tabs will be hidden.
General hints and tips
The internal signals of my modules don't show up in modelsim's wave viewer
Try disabling optimisations when compiling your design : go in Compile -> Compile Options ... and tick "Disable Optimisations by using -O0"
My Yarvi has don't cares (xxxxxxxx) in a register/memory
While Yarvi registers are preinitialised, in simulation memory is not. If you make an uninitialised memory location and read it, for instance:
int a; foo(a);
the value will be 'xxxxxxxx', which will then propagate.
Quartus won't start
- If Quartus sits on the taskbar doing nothing when you start it, and when you click on the icon pops a window saying 'No network connection available', close this window and run Quartus again. It should start second time around.
- If you get an error about licence servers, call a demonstrator (if it is during Labs) or email Simon Moore (simon dot moore at cl dot cam dot ac dot uk). The license server might need rebooting or your PWF machine may have lost the license server information. If it might be the latter, try another machine.
Help! My design doesn't work! What do I do now?
- If you are simulating your design, have you tried adding some more $display statements to trace state updates?
- If you are synthesizing your design:
- have you simulated your design first to check functional correctness?
- have you checked the timing analysis (the Fmax) for your design to ensure it meets timing?
have you included the tpad_pin_assignments.qsf file in your project (is it on the list in Project->Add to Project)? If not, Quartus will see that no pins are connected and optimise your design away to nothingness! In case of doubt, change toplevel.sv to light LEDs in a recognisable pattern.
Argh! I'm never going to get this finished on time!
- Remember that you can do work outside of the ECAD labs sessions. Use the ECAD lab sessions more to get help.
- If you miss sessions (e.g. due to illness) or you really "just don't get it", we can usually help arrange extra supervision in conjunction with your DoS. For most people, however, the help provided in the ECAD lab session is sufficient.
Synthesis/Compilation takes too long!
- Synthesis does take quite some time since Quartus has to find a good solution to several NP-Complete problems. In particular, the place and route phase is very complex for larger designs. We've tried to reduce the need to synthesize designs by making good use of simulation.
Quartus seems to have programmed my FPGA with an old version
In the programming window, check that the program file is set tp <top-level name>.sof in the current project directory. You can check and modify this by double clicking on the filename.