ACS Advanced Computer Design

Altera ROM Example

Note: this ROM implementation is used by the Video Example to provide a font ROM.

This example has a Verilog (VerilogAlteraROM) component which creates and ROM in terms of an array of registers, and initialises the ROM from a memory initialisation file (MIF file). The address is registered which matches the block RAMs on the Cyclone II parts we are using. Parameters for the address width, data width and filename of the MIF file will be modified by the Bluespec Verilog importer file.

/*****************************************************************************
 Paramererised Verilog Altera ROM
 ================================
 Simon Moore

 Verilog stub for Altera's Quartus tools to provide a generic ROM interface
 for AlteraROM.bsv
 *****************************************************************************/

module VerilogAlteraROM(clk, v_addr, v_data, v_en, v_rdy);

   parameter ADDRESS_WIDTH=11;
   parameter MEM_SIZE=(1<<ADDRESS_WIDTH);
   parameter DATA_WIDTH=8;
   parameter FILENAME="your_rom_data.mif";

   input                       clk;
   input [ADDRESS_WIDTH-1:0]   v_addr;
   output reg [DATA_WIDTH-1:0] v_data;
   input                       v_en;
   output reg                  v_rdy;

   (* ram_init_file = FILENAME *) reg [DATA_WIDTH-1:0]   rom [0:MEM_SIZE-1];

   always @(posedge clk) begin
          v_rdy <= v_en;
          if(v_en)
                v_data <= rom[v_addr];
   end

endmodule // Verilog_AlteraROM

The the Bluespec wrapper has two components:

  1. The import "BVI" VerilogAlteraROM part imports the above Verilog including updates to the parameters. The MIF file is specified as a string parameter. Address and data are passed via the simple AlteraROM_Ifc interface. The clock is identified. Inputs and outputs to/from the Verilog are scheduled (C = conflicts, e.g. two read_requests are not allowed in the same cycle).

  2. The mkAlteraROMServer module instantiates the ROM and ensures (via seq_fifo) that responses (reads) happen one or more cycles after the request (address setup).

package AlteraROM;

import GetPut::*;
import ClientServer::*;
import FIFO::*;

interface AlteraROM_Ifc#(type addrT, type dataT);
   method Action read_request(addrT addr);
   method dataT read_response;
endinterface


import "BVI" VerilogAlteraROM =
  module mkAlteraROM #(String filename) (AlteraROM_Ifc#(addrT, dataT))
     provisos(Bits#(addrT, addr_width),
              Bits#(dataT, data_width));
     parameter FILENAME = filename;
     parameter ADDRESS_WIDTH = valueOf(addr_width);
     parameter DATA_WIDTH = valueof(data_width);
     method read_request (v_addr)
        enable (v_en);
     method v_data read_response;
        default_clock clk(clk, (*unused*) clk_gate);
        default_reset no_reset;
        schedule (read_response) SBR (read_request);
        schedule (read_response) C (read_response);
        schedule (read_request) C (read_request);
  endmodule


module mkAlteraROMServer#(String romfile)(Server#(UInt#(11),UInt#(8)));

   AlteraROM_Ifc#(UInt#(11),UInt#(8)) rom <- mkAlteraROM(romfile);
   FIFO#(Bool) seq_fifo <- mkFIFO1;

   interface Put request;
      method Action put(addr);
         rom.read_request(addr);
         seq_fifo.enq(True);
      endmethod
   endinterface
   interface Get response;
      method ActionValue#(UInt#(8)) get;
         seq_fifo.deq;
         let data = rom.read_response();
         return data;
      endmethod
   endinterface
endmodule


endpackage

File location

For the design, see: /usr/groups/ecad-labs/ACS-ACD-1112/bluespec-examples/AlteraROM

Or the public web version: VGA driver and font ROM in Bluespec

CompArch/Teaching/ACS-ACD-1112/Example-AlteraROM (last edited 2011-10-07 14:53:36 by c0245)