Seminar 7: On-chip interconnection networks

As we build increasingly complex parallel systems (e.g. CMPs and MPSoCs) one of the greatest challenges is in providing the interconnection networks that permit the system components to communicate. These must be must be high-performance (low-latency and high-bandwidth), flexible, scalable, simple to design with and power efficient. Beyond simple buses, the idea of an on-chip network illuminates a vast design space for building scalable interconnects.

In this seminar we will discuss the requirements that chip-multiprocessors place on the on-chip network and the trade-offs involved in designing on-chip routers and networks. As we have seen with many other aspects of chip-multiprocessor design, the trade-offs when designing on-chip are very different to those seen in larger parallel machines. Although, much of the existing underlying theory is still relevant.

Lecture Notes

LECTURE NOTES PDF (4up for printing)

Reading group material

  1. "Route Packets, Not Wires: On-Chip Interconnection Networks", William J. Dally and Brian Towles, in Proc. ACM IEEE Design Automation Conference (DAC), pp 684-689, 2001. PDF

  2. "Research challenges for on-chip interconnection networks", John D Owens, William J Dally, Ron Ho, D N Jayasimha, Stephen W Keckler, and Li-Shiuan Peh. IEEE Micro, 27(5):96-108, 2007. PDF

Additional reading

Router Design

Deadlock issues in interconnection networks

On-Chip Networks and Fault Tolerance

Optical On-Chip Networks & Wireless On-Chip Networks

(Carbon nanotubes and Wireless on-chip Networks)

More than one network?

Interconnects for chip-multiprocessors

Rings and the coherence protocol

Crossbar-based interconnects

The MIT RAW Processor:

Earlier Work:


Recent Processors

CompArch/ACS-CMP/Seminar7 (last edited 2017-01-02 14:43:15 by cpc91196-cmbg18-2-0-cust448)