Archive of 2010 version of the course

ACS MPhil Module

Week 1: Divider in Bluespec
Week 2: Cyan Processor
Week 3: Using the Altera NIOS processor
Week 4: Analysis of a ring network
Week 5: MIPS-64 - use and analysis
Deadline: complete the above assignments and submit a portfolio of work (i.e. print-outs of the Bluespec code you have written or modified with the course title and your name on a cover sheet) completed by noon on 8th March. There is an optional oral for this component of the work during the afternoon of the 9th March 2010. You will be allocated a 10 minute time slot.
Final assessment: Suggested mini research projects
Deadline: noon on the 23rd April 2010.

FibSimple - example modules to calculate Fibbonaci numbers (used in week 1)
FibServer - example Servers to calculate Fibbonaci numbers (used in week 1)
ServerFarm - create multiple copies of a Server and multiplex requests and responses to make them look like one server (which should be faster if the server takes multiple clock cycles
Video Example - provides a VGA timing abstraction to generate video on a DE2 board. It also includes two examples including the use of a ROM (for a font) which is imported via some embedded Verilog.
NIOS Custom Instruction Example - an example of a NIOS custom instruction together with abstract interface
Altera ROM Example - example of a ROM as an Altera block RAM preloaded with the contents. It is also an example of how to embed Verilog in Bluespec.

Initialise paths to the tools:
- source /usr/groups/ecad-labs/ACS-ACD-2010/scripts/tools-setup.bash
To use Bluespec, begin with the Bluespec walk through.
To use Altera's Quartus tools, begin with the Part 1b ECAD+Arch lab pages
Information on remote access and machines

Those involved in this course should be signed up to the acd-2010 Google Group. You can register here if you are not already registered.